MILESTONES

CPU, peripherals, and accelerators integrated on a single silicon die — the entire system in one package.

Compact board containing SoC, RAM, and power management. Plugs into a carrier board to form a complete system.

Baseboard that provides IO connectors, power regulation, and peripheral interfaces for a SOM.

Development board built around a reconfigurable FPGA fabric, without a fixed processor architecture.

Umbrella term for any compute unit — CPU, GPU, FPGA, NPU, or AI accelerator.

The hard ARM processor cores embedded inside a Xilinx Zynq device, running software independently of the FPGA fabric.

The reconfigurable FPGA fabric within a Zynq device — implements custom digital logic loaded via a bitstream.

Xilinx SoC families that tightly couple ARM PS cores with FPGA PL fabric on a single chip, enabling hardware–software co-design.

Small, fast on-chip memory blocks distributed throughout FPGA fabric. Used for FIFOs, line buffers, and local data storage.

Larger on-chip FPGA memory. Higher density than BRAM but slightly slower; suited for large frame buffers and lookup tables.

Off-chip DRAM providing high-capacity main memory. Much larger than on-chip BRAM/URAM but with higher latency.

ARM AMBA bus protocol connecting PS and PL in Zynq devices. Variants include AXI-Lite (simple registers), AXI-Full (burst transfers), and AXI-Stream (continuous data flow).

Hardware engine that transfers data between memory regions without CPU involvement, freeing the processor for other work.

Distinct clock regions within an FPGA. CDC techniques (synchronizers, FIFOs) safely transfer signals between regions running at different frequencies.

Configurable digital pins that can be set as input or output under software control. Used for control signals, LEDs, and simple interfaces.

OS with deterministic, bounded response times. Guarantees tasks execute within defined deadlines — essential for mission-critical firmware.

Core OS component managing CPU scheduling, memory, and hardware resources. The Linux kernel is the most common in embedded Linux systems.

A complete deployable OS binary: bootloader + kernel + root filesystem bundled into one artifact for flashing to a device.

Software abstraction layer that controls a specific hardware peripheral, exposing it as a standard interface to higher-level software.

First-stage software that runs after power-on. Initializes clocks, memory, and peripherals before loading and handing off to the OS.

Hardware description file (DTS/DTB) passed to the Linux kernel at boot, describing peripherals, memory maps, interrupt routing, and clocks.

Low-level control code running on embedded processors. Can include FPGA bitstreams, microcontroller programs, and peripheral initialization sequences.

Dedicated hardware H.264/H.265 encoder–decoder block in Xilinx MPSoC devices. Offloads compression from the CPU entirely.

Widely adopted video compression standard. Good balance of quality, efficiency, and decoder availability across all platforms.

Successor to H.264. Roughly 2× compression efficiency at equivalent visual quality — critical for bandwidth-constrained links.

Frame compressed entirely from its own pixel data. No reference to other frames — produces an I-frame, the keyframe of the stream.

Frame compressed using motion-compensated differences from reference frames. P-frames and B-frames achieve much higher compression than I-frames.

Technique estimating a frame's content from past or future reference frames. Encodes only the residual difference, dramatically reducing bitrate.

Ordered sequence of I, P, and B frames forming the repeating encoding unit. GOP size directly affects latency and random-access capability.

Encoded video data rate in bits per second. Governs the quality vs. RF bandwidth trade-off — the primary tuning knob for the link budget.

End-to-end delay from sensor capture to display output. Critical in FPV — every millisecond matters for pilot reaction time.

Hardware or software that compresses (encodes) raw video into a bitstream and decompresses (decodes) it back to displayable frames.

High-speed differential serial interface standard from the MIPI Alliance. The industry-standard physical layer for mobile and embedded camera modules.

Protocol carried over MIPI lanes defining how pixel data, frame sync, and line sync signals are transmitted from sensor to receiver.

Processes raw Bayer sensor data into viewable images. Handles demosaicing, noise reduction, white balance, exposure, and color correction.

The camera imaging chip. Converts incident photons into electrical signals, outputting a Bayer-patterned RAW pixel array.

Data representation of pixel values. RAW — unprocessed Bayer output from the sensor. YUV — luminance plus chrominance, standard for video encoding. RGB — display-ready color triplets.

Medium Access Control layer. Manages channel access, frame formatting, acknowledgements, and retransmission for wireless communication.

Handles modulation, channel coding, and transmission of bits over the air. Implemented in FPGA logic for our SDR-based radio.

Multicarrier modulation technique that divides the spectrum into many orthogonal subcarriers. Foundation of all modern WiFi (802.11a/g/n/ac/ax).

IEEE wireless LAN protocol family. Variants (a/b/g/n/ac/ax) define frequency bands, modulation schemes, and maximum throughput.

Radio system where modulation, filtering, and signal processing are implemented in FPGA or software rather than fixed analog hardware. Enables reprogrammable waveforms.

Digital signal processing chain operating on complex (I/Q) samples before conversion to RF frequencies. Includes FFT, equalization, and channel estimation.

Analog radio section interfacing digital baseband to the antenna. Contains amplifiers (LNA/PA), mixers, filters, and the DAC/ADC boundary.